In my opinion, interfering with step or dir lines, with anything, might not be a good idea. Any logic you put there will just add delay for rise time, logic processing and output, and that could be / might become an issue. These lines are supposed to be sort of realitime, there is no feedback loop for delays on those lines, when the firmware sends a step signal then it considers it executed "as is". If you put delays on them, issues can arise.
Maybe its simpler in your case, maybe inside those black cases might be some TB drivers which are known for reading step signal in a slower manner. Might need step timings in ms while the allegro chips usually in hundreds of us. In general the driver IC might read a step signal differently from one manufacturer to another. Some IC might read a step when the signal goes from low to high and then stays high for a predetermined amount of time, or some other IC might read same thing on the inverse function, on the fall time and if the stays like so again for a certain time. From what i recall some TB (toshiba) drivers, some time back, those needed longer step timings in order to be interpreted correctly.
I dont know how that firmware is, but if you can find some config which would "elongate" the step signal or otherwise some setting for the minimum step interval, those would be my first things to play with. Coz at slow speed it seems ok, but the faster it goes then it appears that it does not read the step signals correctly. Ofc, it would help if you can put a scope on the step line too, coz who knows, maybe some capacitance dont drain out fast enough so a high impedance mode would keep the line high, anyway could be also a hardware issue from your logic, an issue that appears at high frequency only. The hardware side is certainly not out of question. And if you can find the exact IC in those boxes, then read its datasheet about the inputs, maybe it takes 3v3 too for "VIH"? Tried that? In general, i think for the best, if you have 3v3 logic then should use drivers which are advertised to take those levels as signal inputs. In the area of realtime fast freq signals like step line, the idea of level switching to me appears to be very very "less than ideal", sort of speaking.
Maybe its simpler in your case, maybe inside those black cases might be some TB drivers which are known for reading step signal in a slower manner. Might need step timings in ms while the allegro chips usually in hundreds of us. In general the driver IC might read a step signal differently from one manufacturer to another. Some IC might read a step when the signal goes from low to high and then stays high for a predetermined amount of time, or some other IC might read same thing on the inverse function, on the fall time and if the stays like so again for a certain time. From what i recall some TB (toshiba) drivers, some time back, those needed longer step timings in order to be interpreted correctly.
I dont know how that firmware is, but if you can find some config which would "elongate" the step signal or otherwise some setting for the minimum step interval, those would be my first things to play with. Coz at slow speed it seems ok, but the faster it goes then it appears that it does not read the step signals correctly. Ofc, it would help if you can put a scope on the step line too, coz who knows, maybe some capacitance dont drain out fast enough so a high impedance mode would keep the line high, anyway could be also a hardware issue from your logic, an issue that appears at high frequency only. The hardware side is certainly not out of question. And if you can find the exact IC in those boxes, then read its datasheet about the inputs, maybe it takes 3v3 too for "VIH"? Tried that? In general, i think for the best, if you have 3v3 logic then should use drivers which are advertised to take those levels as signal inputs. In the area of realtime fast freq signals like step line, the idea of level switching to me appears to be very very "less than ideal", sort of speaking.